Sequential Circuits Drumtraks - Correction of I/O Address Annotations in the Service Manual
posted on 05 June 2026, updated on 06 June 2026

Summary

During reverse-engineering and hardware verification of a Sequential Circuits Drumtraks, I found that the I/O address annotations printed on the commonly circulated schematic appear to be incorrect.

The actual hardware decoding performed by U214 (74LS138) does not match the annotated addresses shown on the schematic.

This conclusion is based on:

• Continuity measurements on a real Drumtraks motherboard.
• Verification of the LS138 address decoder wiring.
• Verification of all LS138 output destinations.
• Analysis of the OS v0.5 ROM.
• Analysis of the keyboard/LED scan circuitry built around the 4099 latches.

Hardware Verification

U214 Address Decoder

U214 is a HD74LS138P (standard 74LS138).

Continuity measurements performed directly on the motherboard confirm:

The /M1 path was verified:

Z80 pin 27 (/M1)
    ->
74LS04 pin 5
74LS04 pin 6
    ->
U214 pin 5 (/G2B)

Therefore the LS138 is enabled only during I/O cycles and not during instruction fetches.

Additional Documentation Discrepancy (U212 74LS04)

During hardware verification, an inconsistency was found between the published schematic annotations and the actual motherboard wiring around U212 (74LS04).

Continuity measurements performed on the physical PCB showed:

Z80 /M1 (pin 27)
    ->
U212 pin 5
U212 pin 6
    ->
U214 (/G2B)

This confirms that inverter section 5→6 is used in the I/O decode enable path.

Additional measurements showed:

U216 pin 12
    ->
U212 pin 13
U212 pin 12
    ->
CC OUT (via R222)

This confirms that inverter section 13→12 is used in the CC OUT signal path.

The published schematic annotations appear to interchange these two inverter sections.

Although this discrepancy does not affect functionality, it demonstrates that at least one documentation error exists in the available schematic set.

For this reason, all conclusions presented in this document are based primarily on direct continuity measurements and verified logic decoding rather than on the printed schematic annotations alone.